1. Field of the Invention
The present invention is in the field of hardware and software for data packet routers and pertains particularly to methods for improving data processing rates within the router fabric of such data packet routers.
2. Discussion of the State of the Art
With the advent and continued development of the well-known Internet network, and of similar data-packet networks, much attention has been paid to computing machines for receiving, processing, and forwarding data packets. Such computing machines, known as routers in the art, typically have multiple interfaces for receiving and sending packets, and circuitry coupled at each interface, including typically a packet processor, for handling and processing packets. The circuitry at the interfaces is typically implemented on modules known as line cards in the art, and all of the line cards are typically interconnected. In systems known to the present inventor interconnection is through what is known as the internal fabric, which comprises interconnected fabric cards.
A fabric card known to the inventor supports a plurality of ingress/egress data ports and a crossbar switching facility for switching traffic in the card from port to port. The ports and switching facility are implemented in the form of ASIC chips that are typically clocked in a synchronous mode according to a master clock signal.
The switching facility of the above-described fabric card is a bit-sliced ASIC partitioned into several identical slices known as cross-point ASICS (CPAs). Each slice is adapted to handle switched transmission of a bit portion of each data packet received from a sending port that is transmitting data destined for another port. Also included in this facility is a chip (ASIC) adapted to schedule communication between the ports on the card. This ASIC is termed a cross-point scheduling ASIC (CSA). This scheduling is accomplished, basically, on a per-request basis wherein a port issues a request to transmit on the card to a destination (another port) through the switching facility. When it is determined by the scheduling chip that the switching facility can support the switching and transmission of data (from ingress to egress), a grant is issued to the requesting port. The scheduling chip also programs each bit-slice of the facility to receive from the requesting port and to transmit to the receiving port.
The present apparatus and method known to the inventor operates in a manner that slices of a single packet are required to be sent synchronously, which imposes a unnecessary upper operating frequency limitation due to clock offset among clocked components. What is clearly needed is an apparatus and a method for managing data flow through a bit-sliced switching facility on a router fabric card that allows the CPAs to be used in a pseudo-synchronous way, improving the efficiency of use of the transmission mechanism.